1 ? fn7278.2 el7154 high speed, monolithic pin driver the el7154 three-state pin driver is particularly well suited for ate and level shifting applications. the 4a peak drive capability, makes the el7154 an excellent choice when driving high speed capacitive lines. the p-channel mosfet is completely isolated from the power supply, providing a high degree of flexibility. pin (7) can be grounded, and the output can be taken from pin (8) when a ?source follower? output is desired. the n-channel mosfet has an isolated drain, but shares a common bus with pre-drivers and level shifter circuits. this is necessary to ensure that the n-channel device can turn off effectively when v l goes below gnd. in some power-fet and igbt applications, negative drive is desirable to insure effective turn-off. the el7154 can be used in these applications by returning v l to a moderate negative potential. pinout manufactured under u.s. patent nos. 5,334,883, #5,341,047, #5,352,578, #5,352,389, #5,351,012, #5,374,898 features ? comparatively low cost ? three-state output ? 3v and 5v input compatible ? clocking speeds up to 10mhz ? 20ns switching/delay time ? 4a peak drive ? isolated drains ? low output impedance: 2.5 ? low quiescent current: 5ma ? wide operating voltage: 4.5v to16v ? isolated p-channel device ? separate ground and v l pins ? pb-free plus anneal available (rohs compliant) applications ? loaded circuit board testers ? digital testers ? level shifting below gnd ?igbt drivers ? ccd drivers truth table three-state input p out n out 0 0 open open 0 1 open open 1 0 high open 1 1 open low vl el7154 (8 ld pdip, 8 ld soic) top view 1 2 3 45 6 7 8 level shift and logic vdd three-state input gnd vl vl nout pout vh data sheet march 8, 2007 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 1996, 2005, 2007. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn7278.2 march 8, 2007 ordering information part number part marking tape and reel package pkg. dwg. # el7154cn el7154cn - 8 ld pdip mdp0031 EL7154CNZ el7154cn z - 8 ld pdip* (pb-free) mdp0031 el7154cs 7154cs - 8 ld soic mdp0027 el7154cs-t7 7154cs 7? 8 ld soic mdp0027 el7154cs-t13 7154cs 13? 8 ld soic mdp0027 el7154csz (see note) 7154csz - 8 ld soic (pb-free) mdp0027 el7154csz-t7 (see note) 7154csz 7? 8 ld soic (pb-free) mdp0027 el7154csz-t13 (see note) 7154csz 13? 8 ld soic (pb-free) mdp0027 *pb-free pdips can be used for through hole wave solder processing only. they are not in tended for use in reflow solder process ing applications. note: intersil pb-free plus anneal products employ special pb-free material sets ; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. nominal operating voltage range pin min max v l -3 0 v dd to v l 515 v h to v l 215 v dd to v h -0.5 15 v dd 515 el7154
3 fn7278.2 march 8, 2007 absolute maxi mum ratings (t a = +25c) thermal information supply (v dd to v l ; v h to v l , v h to gnd), v+ to v h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5v v l to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5v input pins . . . . . . . . . . . . . . . . . -0.3v below v l to +0.3v above v dd peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4a storage temperature range . . . . . . . . . . . . . . . . . .-65c to +150c ambient operating temperature . . . . . . . . . . . . . . . .-40c to +85c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . +125c power dissipation soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mw pdip* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mw pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp *pb-free pdips can be used for through hole wave solder processing only. they are not intended for use in reflow solder processing applications caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications t a = +25c, v dd = +12v, v h = +12v, v l = -3v, unless otherwise specified. parameter description test conditions min typ max units input v ih logic ?1? input voltage 2.4 v i ih logic ?1? input current v ih = v dd 0.1 10 a v il logic ?0? input voltage 0.6 v i il logic ?0? input current v il = 0v 0.1 10 a v hvs input hysteresis 0.3 v output r oh pull-up resistance i out = -100ma 1.5 4 r ol pull-down resistance i out = +100ma 2 4 i out output leakage current v dd /gnd 0.2 10 a i pk peak output current source/sink 4.0 a i dc continuous output current source/sink 200 ma power supply i s power supply current inputs = v dd 12.5ma v s operating voltage 4.5 16 v i g current to gnd (pin 4) 1 10 a i h off leakage at v h pin 8 = 0v 1 10 a ac electrical specifications t a = +25c unless otherwise specified parameter description test conditions min typ max units switching characteristics (v dd = v h = 12v; v l = -3v) t r rise time c l = 100pf 4 25 ns c l = 2000pf 20 t f fall time c l = 100pf 4 25 ns c l = 2000pf 20 t d-1 turn-off delay time c l = 2000pf 20 25 ns t d-2 turn-on delay time c l = 2000pf 10 25 ns t d-1 three-state delay 25 ns t d-2 three-state delay 25 ns el7154
4 fn7278.2 march 8, 2007 timing table standard test configuration el7154
5 fn7278.2 march 8, 2007 typical performance curves figure 1. max power derating curves figure 2. switch thr eshold vs supply voltage figure 3. input current vs voltage figure 4. peak drive vs supply voltage figure 5. quiescent supply current figure 6. ?on? resistance vs supply voltage figure 7. average supply current vs voltage and frequency figure 8. rise/fall time vs load el7154
6 fn7278.2 march 8, 2007 typical applications figure 9. pin driver figure 10. adjustable amplitude pulse generator figure 11. igbt driver with negative swing figure 12. pmds follower figure 13. resonant gate driver el7154
7 fn7278.2 march 8, 2007 el7154 small outline package family (so) gauge plane a2 a1 l l1 detail x 4 4 seating plane e h b c 0.010 b m ca 0.004 c 0.010 b m ca b d (n/2) 1 e1 e n n (n/2)+1 a pin #1 i.d. mark h x 45 a see detail ?x? c 0.010 mdp0027 small outline package family (so) symbol inches tolerance notes so-8 so-14 so16 (0.150?) so16 (0.300?) (sol-16) so20 (sol-20) so24 (sol-24) so28 (sol-28) a 0.068 0.068 0.068 0.104 0.104 0.104 0.104 max - a1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - a2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - d 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 e 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - e1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 basic - l 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - l1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 reference - n 8 14 16 16 20 24 28 reference - rev. m 2/07 notes: 1. plastic or metal protrusions of 0.006? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions ?d? and ?e1? are measured at datum plane ?h?. 4. dimensioning and tolerancing per asme y14.5m - 1994
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn7278.2 march 8, 2007 el7154 plastic dual-in-line packages (pdip) mdp0031 plastic dual-in-line package symbol inches tolerance notes pdip8 pdip14 pdip16 pdip18 pdip20 a 0.210 0.210 0.210 0.210 0.210 max a1 0.015 0.015 0.015 0.015 0.015 min a2 0.130 0.130 0.130 0.130 0.130 0.005 b 0.018 0.018 0.018 0.018 0.018 0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 d 0.375 0.750 0.750 0.890 1.020 0.010 1 e 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 e1 0.250 0.250 0.250 0.250 0.250 0.005 2 e 0.100 0.100 0.100 0.100 0.100 basic ea 0.300 0.300 0.300 0.300 0.300 basic eb 0.345 0.345 0.345 0.345 0.345 0.025 l 0.125 0.125 0.125 0.125 0.125 0.010 n 8 14 16 18 20 reference rev. c 2/07 notes: 1. plastic or metal protrusions of 0.010? maximum per side are not included. 2. plastic interlead protrusions of 0.010? maximum per side are not included. 3. dimensions e and ea are measured with the leads constrained perpendicular to the seating plane. 4. dimension eb is measured wi th the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. d l a e b a1 note 5 a2 seating plane l n pin #1 index e1 12 n/2 b2 e eb ea c
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